Does a process switch affect std::atomic compare and exchange in arm9 processor?

I am new to std::atomic in c++ and trying to understand the implementation of compare and exchange operations under ARM processors.I am using gcc on linux.

When i look into the assembly code

    mcr p15, 0, r0, c7, c10, 5
.L41:
    ldrexb  r3, [r2]
    cmp r3, r1
    bne .L42
    strexb  ip, r0, [r2]
    cmp ip, #0
    bne .L41
.L42:
    mcr p15, 0, r0, c7, c10, 5

My understanding is

1. it takes multiple instructions to do compare and exchange.
2. ldrex marks the memory location as exclusive and reads the data.
3. strex stores the data and clears the exclusive flag for that location.

My questions are

1. does ldrex mark the Virtual addr. as exclusive or the physical address?

2. If Process P1 marks the virtual address as exclusive and a process switch occurs to P2, will that virtual addr. be accessible in P2? what will happen if P2 also execute an ldrex on the same address.

3. If Process P1 marks the physical address as exclusive and a process switch occurs, when P1 resumes isn't there a chance that the data now resides in a different location in physical memory due to paging.

I am trying to understand this because, i want to do a compare and exchange on a shared memory location accessed by multiple processes.