I am using Vivado HLS 2018.2 to design an FPGA, and I have verified my design with C-simulation. However, when I run C synthesis to get a resource utilization report, I get the following error.
In file included from /opt/Xilinx/Vivado/2018.2/lnx64/tools/gcc/lib/gcc/x86_64-unknown-linux-gnu/4.6.3/../../../../include/c++/4.6.3/array:34:
/opt/Xilinx/Vivado/2018.2/lnx64/tools/gcc/lib/gcc/x86_64-unknown-linux-gnu/4.6.3/../../../../include/c++/4.6.3/bits/c++0x_warning.h:32:2: error: This file requires compiler and library support for the upcoming ISO C++ standard, C++0x. This support is currently experimental, and must be enabled with the -std=c++0x or -std=gnu++0x compiler options.
#error This file requires compiler and library support for the upcoming \
^
1 error generated.\n
C preprocessor failed.
If it's a compiler problem, how did the C simulation run perfectly? Moreover, I have added std=c++0x
to the input arguments to the compiler (Project>Project Settings>Simulation>Input Arguments), yet I get the same error when running synthesis. I also tried editing the script.tcl file for the project by adding -argv {std=c++0x}
to the csynth_design and csim_design commands. Please help if you know a solution or a workaround to this. Thanks.
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