Let’s say I have hardware on which all the accesses to memory for a value less or equal to size of bool
are thread-safe, and consistency issues in regards to caching are avoided because of the hardware or the code.
Should I expect that non-atomic access from multiple threads will be compiled just as the code was single-threaded and so I get the thread-safe program for the platform?
The question is FAQ-style, see my answer for it: https://stackoverflow.com/a/69062080/1790694
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